Phase change memory with flexible time-based cell decoding

ABSTRACT

Methods and systems for time-based cell decoding for PCM memory. Generally, the higher the PCM element resistance, the longer it takes for a read output to change state. PCM memory output is determined using differentiated timings of read outputs changing state, rather than differentiated values of read outputs. In some single-bit single-ended sensing embodiments, a reference, with resistance between the resistances corresponding to a pair of adjacent logical states, is stored in multiple reference cells; a “vote” unit emits a clock signal when a majority of the reference cell read outputs transition at the vote unit. Timing units produce different binary outputs depending on whether a data read output or the clock signal changes state first at the timing unit. Time-based decoding provides advantages including improved temperature and drift resilience, improved state discrimination, improved reliability of multibit PCM, and fast and reliable sensing.

CROSS-REFERENCE

Priority is claimed from Provisional Patent Application No. 61/816,045,which is hereby incorporated by reference.

The following four applications, including the present application,share a common assignee, all have a common effective filing date (andare therefore co-pending), and share at least some overlappinginventorship. All of these applications, and all of their direct andindirect parent applications, are hereby incorporated by reference: USapplication ______ filed herewith (Atty. Docket No.: BAM-131); USapplication ______ filed herewith (Atty. Docket No.: BAM-157); USapplication ______ filed herewith (Atty. Docket No.: BAM-177); and USapplication filed herewith (Atty. Docket No.: BAM-182). Applicantreserves the right to claim priority back to all of these, in the USand/or in any other country where such priority can legally be claimed.

BACKGROUND

The present application relates to systems, devices and methods formemory access operations involving phase change memory units.

Note that the points discussed below may reflect the hindsight gainedfrom the disclosed inventions, and are not necessarily admitted to beprior art.

Phase change memory (“PCM”) is a relatively new nonvolatile memorytechnology, which is very different from any other kind of nonvolatilememory. First, the fundamental principles of operation, at the smallestscale, are different: no other kind of solid-state memory uses areversible PHYSICAL change to store data. Second, in order to achievethat permanent physical change, an array of PCM cells has to allow read,set, and reset operations which are all very different from each other.The electrical requirements of the read, set, and reset operations makethe peripheral circuit operations of a PCM very different from those ofother nonvolatile memories. Obviously some functions, such addressdecoding and bus interface, can be the same, but the closest-in parts ofthe periphery, which perform set, reset, and read operations on an arrayor subarray, must satisfy some unique requirements.

The physical state of a PCM cell's memory material is detected asresistance. For each selected cell, its bitline is set to a knownvoltage, and the cell's access transistor is turned on (by theappropriate wordline). If the cell is in its low-resistance state, itwill sink a significant current from the bit line; otherwise, it willnot.

Set and Reset operations are more complicated. Both involve heat. Asdiscussed below, a “set” operation induces the memory material torecrystallize into its low-resistance (polycrystalline) state, while a“reset” operation anneals the memory material into its high-resistance(amorphous) state.

Write operations (Set and Reset) normally have more time budget thanread operations. In read mode a commercial PCM memory should becompetitive with the access speed (and latency if possible) of astandard DRAM. If this degree of read speed can be achieved, PCM becomesvery attractive for many applications.

The phase change material is typically a chalcogenide glass, usingamorphous and crystalline (or polycrystalline) phase states to representbit states.

A complete PCM cell can include, for example: a top electrode (connectedto the bit line), a phase change material (e.g. a chalcogenide glass), aconductive pillar which reaches down from the bottom of the phase changematerial, an access transistor (gated by a word line), and a bottomconnection to ground. The phase change material can extend over multiplecells (or over the whole array), but the access transistors arelaterally isolated from each other by a dielectric.

FIG. 2A shows an example of a PCM element 2010. A top electrode 2020overlies a phase change material 2030, e.g. a chalcogenide glass. Notethat material 2030 also includes a mushroom-shaped annealed zone(portion) 2070 within it. (The annealed zone 2070 may or may not bepresent, depending on what data has been stored in this particularlocation.) The annealed zone 2070, if present, has a much higherresistivity than the other (crystalline or polycrystalline) parts of thematerial 2030.

A conductive pillar 2050 connects the material 2030 to a bottomelectrode 2040. In this example, no selection device is shown, though inpractice, an access transistor would normally be connected in serieswith the phase change material. The pillar 2050 is embedded in aninsulator layer 2060.

When voltage is applied between the top 2020 and bottom 2040 electrodes,the voltage drop will appear across the high-resistivity zone 2070 (ifpresent). If sufficient voltage is applied, breakdown will occur acrossthe high-resistivity zone. In this state the material will become veryconductive, with large populations of mobile carriers. The material willtherefore pass current, and current crowding can occur near the top ofthe pillar 2050. The voltage which initiates this conduction is referredto as the “snapback” voltage, and FIG. 2C shows why.

FIG. 2C shows an example of instantaneous I-V curves for a device likethat of FIG. 2A, in two different states. Three zones of operation aremarked.

In the zone 2200 marked “READ,” the device will act either as a resistoror as an open (perhaps with some leakage). A small applied voltage willresult in a state-dependent difference in current, which can bedetected.

However, the curve with open circles, corresponding to the amorphousstate of the device, shows some more complex behaviors. The two curvesshow behaviors under conditions of higher voltage and higher current.

If the voltage reaches the threshold voltage V_(th), current increasesdramatically without any increase in voltage. (This occurs whenbreakdown occurs, so the phase-change material suddenly has a largepopulation of mobile carriers.) Further increases in applied voltageabove V_(th) result in further increases in current; note that thisupper branch of the curve with hollow circles shows a lower resistancethan the curve with solid squares.

If the applied voltage is stepped up to reach the zone 2150, thebehavior of the cell is now independent of its previous state.

When relatively large currents are applied, localized heating will occurat the top of the pillar 2050, due to the relatively high currentdensity. Current densities with typical dimensions can be in the rangeof tens of millions of Amperes per square cm. This is enough to producesignificant localized heating within the phase-change material.

This localized heating is used to change the state of the phase-changematerial, as shown in FIG. 2B. If maximum current is applied in a verybrief pulse 2100 and then abruptly stopped, the material will tend toquench into an amorphous high-resistivity condition; if the phase-changematerial is cooled more gradually and/or not heated as high as zone2150, the material can recrystallize into a low-resistivity condition.Conversion to the high-resistance state is normally referred to as“Reset”, and conversion to the low-resistance state is normally referredto as “Set” (operation 2080). Note that, in this example, the Set pulsehas a tail where current is reduced fairly gradually, but the Resetpulse does not. The duration of the Set pulse is also much longer thanthat of the Reset pulse, e.g. tens of microseconds versus hundreds ofnanoseconds.

FIG. 2D shows an example of temperature versus resistivity for variousPCM materials. It can be seen that each curve has a notable resistivitydrop 2210 at some particular temperature. These resistivity dropscorrespond to phase change to a crystalline (or polysilicon) state. Ifthe material is cooled gradually, it remains in the low resistivitystate after cooling.

In a single-bit PCM, as described above, only two phases aredistinguished: either the cell does or does not have a significanthigh-resistivity “mushroom cap” 2070. However, it is also possible todistinguish between different states of the mushroom cap 2070, andthereby store more than one bit per cell.

FIG. 2E shows an equivalent circuit for an “upside down” PCM cell 2010.In this example the pass transistor 2240 is gated by Wordline 2230, andis connected between the phase-change material 2250 and the bitline2220. (Instead, it is somewhat preferable to connect this transistorbetween ground and the phase-change material.

FIG. 2F shows another example of a PCM cell 2010. A bitline 2220 isconnected to the top electrode 2020 of the phase-change material 2250,and transistor 2240 which is connected to the bottom electrode 2030 ofthe PCM element. (The wordline 2230 which gates the vertical transistor2240 is not shown in this drawing.) Lines 2232, which are shown asseparate (and would be in a diode array), may instead be a continuoussheet, and provide the ground connection.

FIG. 2G shows an example of resistance (R) over time (t) for a singlePCM cell following a single PCM write event at time t=0. The resistancecurve 2400 for a cell which has been reset (i.e. which is in itshigh-resistance state) may rise at first, but then drifts significantlylower. The resistance curve 2410 for a cell in the Set state is muchflatter. The sense margin 2420, i.e., the difference between set andreset resistances, also decreases over time. Larger sense marginsgenerally result in more reliable reads, and a sense margin which is toosmall may not permit reliable reading at all. 2G represents theapproximate behavior of one known PCM material; other PCM materialcompositions may behave differently. For example, other PCM materialcompositions may display variation of the set resistance over time.

The downwards drift of reset resistance may be due to, for example,shrinking size of the amorphous zone of the phase-change material, dueto crystal growth; and, in some cells, spontaneous nucleation steepeningthe drift curve (possibly only slightly) due to introducing furtherconductive elements into the mushroom-shaped programmable region.

FIG. 2H shows an example of a processing system 2300. Typically, aprocessing system 2300 will incorporate at least some of interconnectedpower supplies 2310, processor units 2320 performing processingfunctions, memory units 2330 supplying stored data and instructions, andI/O units 2340 controlling communications internally and with externaldevices 2350.

FIG. 2I shows an example of a PCM single-ended sensing memory. Twodifferent PCM cells 2400 on different ends of a sense amplifier can beselected separately. Selected elements 2410 are separately sensed by asingle-ended sense amplifier 2420.

FIG. 2J shows an example of a known PCM single-ended sense amplifier2500. Generally, in a single-ended sense amplifier, a cell read outputconducted by a selected bitline BLB is compared against a referencecurrent to provide a digital output OUT. When the PRECHARGE signal turnson transistor 2530, voltage V04 (e.g., 400 mV) precharges the bitlineBLB. After precharge ends, the READ signal turns on transistor 2550.Transistor 2550 is connected, through source follower 2560 and load2580, to provide a voltage which comparator 2600 compares toVoltage_REF, to thereby generate the digital output OUT.

A variety of nonvolatile memory technologies have been proposed overrecent decades, and many of them have required some engineering toprovide reference values for sensing. However, the requirements andconstraints of phase-change memory are fundamentally different fromthose of any other kind of nonvolatile memory. Many memory technologies(such as EEPROM, EPROM, MNOS, and flash) test the threshold voltage ofthe transistor in a selected cell, so referencing must allow for thetransistor's behavior. By contrast, phase-change memory simply sensesthe resistance of the selected cell. This avoids the complexities ofproviding a reference which will distinguish two (or more) possibilitiesfor an active device's state, but does require detecting a resistancevalue, and tracking external variations (e.g. temperature and supplyvoltage) which may affect the instantaneous value of that resistance.

The possibility of storing more than one bit of data in a singlephase-change material has also been suggested. Phase-change memoriesimplementing such architectures are referred to here as “multibit” PCMs.If the “Set” and/or “Reset” operations can be controlled to producemultiple electrically distinguishable states, then more than one bit ofinformation can be stored in each phase-change material location. It isknown that the current over time profile of the Set operation can becontrolled to produce electrically distinguishable results, though thiscan be due to more than one effect. In the simplest implementation,shorter anneals—too short to produce full annealing of the amorphouslayer—can be used to produce one or more intermediate states. In somematerials, different crystalline phases can also be produced byappropriate selection of the current over time profile. However, what isimportant for the present application is merely that electricallydistinguishable states can be produced.

For example, if the complete layer of phase-change material can havefour possible I/V characteristics, two bits of information can be storedin each cell—IF the read cycle can accurately distinguish among the fourdifferent states.

(The I/V characteristics of the cells which are not in the fully Setstate are typically nonlinear, so it is more accurate to distinguish thestates in terms of current flow at a given voltage; resistance is oftenused as a shorthand term, but implies a linearity which may not bepresent.)

In order to make use of the possible multibit cell structures, it isnecessary to reliably distinguish among the possible states. To makethis distinction reliably, there must be some margin of safety, despitethe change in characteristics which may occur due to history,manufacturing tolerances, and environmental factors. Thus, the readarchitecture of multibit PCMs is a far more difficult challenge than itis for PCMs with single-bit cells.

SUMMARY

The present application discloses new phase change memory (PCM)architectures, devices, arrays, subarrays, systems, and methods. Theinventors have discovered that, surprisingly, PCM cell read outputs canbe decoded by time-domain gating of the state change coming out of thesense amplifiers. Preferably one or more reference cells are connectedto generate a transition, at the sense amplifier(s) connected to thereference cell(s), which is intermediate between the times when thedifferent possible stored states generate their transitions. Thisreference transition then gates propagation of the state of the othersense amplifiers.

In one disclosed class of novel embodiments, this architecture isapplied for reading multilevel PCM cells.

In another disclosed class of novel embodiments, a “majority voting”architecture is used to generate the reference transition.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosed inventions will be described with reference to theaccompanying drawings, which show important sample embodiments and whichare incorporated in the specification hereof by reference, wherein:

FIG. 1A schematically shows an example of a PCM memory.

FIG. 1B shows an example of a timing diagram for PCM memory reads.

FIG. 1C shows an example of gate logic for a 3-to-1 Vote unit.

FIG. 2A shows an example of a PCM element.

FIG. 2B shows an example of PCM bit line signals.

FIG. 2C shows an example of voltage versus current in a PCM material.

FIG. 2D shows an example of temperature versus resistance in a PCMmaterial.

FIG. 2E shows an example of a PCM cell.

FIG. 2F shows an example of a PCM cell.

FIG. 2G shows an example of resistance over time for a PCM cell.

FIG. 2H shows an example of a processing system.

FIG. 2I shows an example of a PCM single-ended sensing memory.

FIG. 2J shows an example of a known PCM single-ended sense amplifier.

FIG. 3 schematically shows an example of a PCM memory.

FIG. 4A schematically shows an example of a PCM memory.

FIG. 4B shows an example of a timing diagram for PCM memory reads.

FIG. 5 schematically shows an example of a PCM memory.

FIG. 6A schematically shows an example of a PCM memory.

FIG. 6B shows an example of a timing diagram for PCM memory reads.

DETAILED DESCRIPTION OF SAMPLE EMBODIMENTS

The numerous innovative teachings of the present application will bedescribed with particular reference to presently preferred embodiments(by way of example, and not of limitation). The present applicationdescribes several inventions, and none of the statements below should betaken as limiting the claims generally.

Examples of implementations for single-bit PCM are described first, butit will be understood that multibit embodiments present additionaladvantages including increased storage density and attractive synergieswith the present inventions.

The present application discloses new phase change memory (PCM)architectures, devices, arrays, subarrays, systems, and methods. Theinventors have discovered that, surprisingly, PCM cell read outputs canbe decoded by time-domain gating of the state change coming out of thesense amplifiers. Preferably one or more reference cells are connectedto generate a transition, at the sense amplifier(s) connected to thereference cell(s), which is intermediate between the times when thedifferent possible stored states generate their transitions. Thisreference transition then gates propagation of the state of the othersense amplifiers. Time-based decoding enables use of fast, accuratesensing that provides a wide array of synergies with multibit PCM andwith various PCM memory features that help maintain sensing accuracydespite resistance drift.

Generally, the higher a PCM cell's resistance, the longer it takes forthe cell's read output to change state. State change timing informationis preserved by timing units. For two read outputs configured to bereceived by a single timing unit, the PCM cell corresponding to the readoutput that transitions first has lower resistance (e.g., a Setresistance) than the PCM cell corresponding to the read output thattransitions second (e.g, a Reset resistance).

Reference resistances can be used during memory reads to discriminatebetween, for example, resistances corresponding to pairs of adjacentlogical states. For example, a reference resistance can be between theresistances corresponding to a pair of adjacent logical states.

The inventors have also discovered that, surprisingly, read reliabilitycan be improved by storing such an intermediate reference in multiplereference cells and, when a majority of the reference cell read outputsreach a “vote” unit, propagating a clock signal to timing units. Readoutputs are also propagated to timing units. The output of a timing unitconfigured to receive a clock signal and a read output depends onwhether the clock signal or the read output changes state first.Generally, different timing units receive a different read output and/ora different clock signal.

In single-ended sensing embodiments, decoded read outputs depend onwhether the read outputs of data-storing cells, or of reference-storingcells (or a corresponding clock signal), change state first.

In differential sensing embodiments, n-state phase change memory cellsare organized into groups of n cells, each cell in a group storing adifferent state. A group of cells collectively encodes one of n!possible states. The collective state encoded by a group of cells isdecoded by determining the order in which the read outputs of the cellsin the group change state.

The disclosed innovations, in various embodiments, provide one or moreof at least the following advantages. However, not all of theseadvantages result from every one of the innovations disclosed, and thislist of advantages does not limit the various claimed inventions.

-   -   Provides more accurate memory reads;    -   lessens error correction requirements;    -   improves temperature tolerance;    -   improves resistance drift tolerance;    -   enables synergies with various memory features that improve        resistance drift tolerance;    -   facilitates use of multibit PCM;    -   facilitates effective use of higher-density storage        configurations;    -   enables using a single sense amplifier design for a variety of        single-bit, multi-bit, single-ended sensing and differential        sensing architectures;    -   enables switching between data storage schemes (e.g.,        single-ended or differential sensing, and single-bit or multibit        PCM);    -   facilitates broadly flexible and/or mode-switchable architecture        design;    -   simplifies sensing architecture;    -   reduces sensing architecture size;    -   reduces manufacturing complexity; and/or    -   faster reads.

In preferred embodiments, the voltage on a bitline at a given timedepends on the resistance of the PCM cell being read by that bitline.Bitlines reading PCM cells with lower resistances reach a target voltageearlier than bitlines reading PCM cells with higher resistances. Senseamplifiers change output state when corresponding bitlines reach thetarget voltage. Sense amplifier output state change times thereforedepend on the resistances of corresponding PCM cells being read.

Sense amplifier outputs that change state earlier transition at timingunits earlier. Timing units latch binary output values (i.e., 0 or 1)depending on the order in which sense amplifier outputs transition atthe timing units. Timing unit binary outputs can correspond to PCMmemory outputs, or can be decoded to produce PCM memory outputs.

In some single-ended sensing single-bit PCM embodiments, bitlinesreading data-storing PCM cells (data cells) with lower resistance (e.g.,a Set resistance) reach a target voltage faster than bitlines readingdata cells with higher resistance (e.g., a Reset resistance). Threebitlines reading reference-storing PCM cells (reference cells) reach thetarget voltage in an intermediate amount of time. Sense amplifiersgenerate outputs when corresponding bitlines reach the target voltage. A3-to-1 vote unit outputs a clock signal when a majority (two) of thesense amplifier outputs corresponding to reference cells transition atthe vote unit. Timing units are configured to receive this clock signaland a sense amplifier output corresponding to a data cell. If the clocksignal is first to transition at a timing unit, then the correspondingdata cell has a higher resistance than the reference cells, and thetiming unit latches a binary output (e.g., a 0). If the sense amplifieroutput is first to transition at the timing unit, then the correspondingdata cell has a lower resistance than the reference cells, and thetiming unit latches a different binary output (e.g., a 1).

In some single-ended sensing multibit PCM embodiments, multiple 3-to-1vote units are used, with multiple different references discriminatingdifferent pairs of adjacent logical states. For n-state PCM, differentones of n−1 3-to-1 vote units each produce a different clock signal ontransition of a majority (two) of the sense amplifier outputscorresponding to one of n−1 different references. Generally, a senseamplifier output corresponding to a data cell will be received by n−1timing units, different ones of the n−1 timing units receiving differentclock signals. The state of the data cell can be decoded (e.g., byspecialized decoding logic) based on the order in which a correspondingsense amplifier output and the n−1 clock signals each transition atcorresponding timing units.

In some differential sensing single-bit PCM embodiments, a timing unitreceives two sense amplifier outputs, corresponding to two differentdata cells storing complementary binary values. Bitline and senseamplifier operation can be similar to the single-ended sensingsingle-bit PCM embodiments described above. The sense amplifier outputthat transitions first at the timing unit corresponds to the data cellwith the lower resistance.

In some differential sensing multibit PCM embodiments, for n-state PCM,the collective state encoded by a group of n data cells can be decodedusing 1+2+ . . . +n−1 timing units receiving the various possible pairsof n sense amplifier outputs. Timing unit binary outputs depend on theorder in which sense amplifier outputs transition at the timing units.The binary outputs of the timing units can be further decoded (e.g., byspecialized decoding logic), e.g., to reproduce the values with whichthe group was written, or, for multiple groups, to reproduce the writeinput that caused the groups to be written.

In differential decoding, PCM cells are arranged in groups of n PCMcells, and individual PCM cells in a group store different ones of ndifferent logical states. Groups of PCM cells thus encode one of n! (nfactorial) different collective states.

In preferred embodiments, sense amplifiers perform a voltage to timeconversion. When a bitline voltage that was charged to a prechargevoltage (V_(pre)) discharges to a sensing threshold voltage (V_(thr))(the target voltage), the output of a sense amplifier connected to sensethe bitline changes state (which can also be viewed as the senseamplifier generating an output). This state change occurs AT APARTICULAR TIME that is primarily dependent on the resistance stored bythe PCM cell being read, thus indicating the stored contents of the PCMcell. This timing information is preserved by propagating the senseamplifier output to a timing unit. Timing units receive at least twosense amplifier outputs configured to change state (and therefore,generally, to transition at timing units) at different times. Timingunits latch different outputs (e.g., binary outputs) depending on theorder in which sense amplifier outputs transition at correspondingtiming units. Timing unit outputs can be used to determine what data waswritten to and stored by corresponding PCM cells being read.

The amount of time it takes for a bitline voltage to drop from V_(pre)to V_(thr) depends on the resistance and capacitance of that bitline.The resistance and capacitance of a bitline reading a PCM cell includesthe resistance and capacitance of that PCM cell. It is generallypreferable that capacitance be the same (or nearly the same) on allbitlines reading PCM cells, effectively making bitline capacitance aconstant. If bitline capacitance is a constant, then the resistance ofthe PCM cell being read is the predominant variable determining the timefor a bitline to discharge from V_(pre) to V_(thr).

The resistance-based read time is a result of the time taken todischarge the bitline capacitance through the bitline resistance. The RCtime constant equation for this discharge time is generally a usable(but not perfect) model of this behavior in a PCM context:

$\begin{matrix}{{v(t)} = {1 - ^{{- \frac{1}{\tau}}t}}} & {{Equation}\mspace{14mu} 1}\end{matrix}$

Here, V(t) is the proportion of a target voltage reached by a circuitbeing continuously discharged (or charged) at time t after discharge (orcharge) begins, and τ (tau) is R*C, where R is the bitline resistanceand C is the bitline capacitance.

In some embodiments, when a read access begins, all bitlines (and,consequently, the PCM cells being read) are charged to a prechargevoltage V_(pre). A time margin can be provided for precharge (e.g., 150%of the minimum time required for approximately full precharge) to ensurefull or nearly-full precharge voltage. Nearly-full precharge voltage isgenerally acceptable, because sensing (decoding) is by comparisonbetween state change timings resulting from bitlines precharged toessentially the same full or nearly-full precharge voltage.

After the bitlines are precharged, the voltage clamp forcing thebitlines to a voltage source's voltage level is released, and thebitlines begin to discharge. Voltage on bitlines reading PCM cells withhigh resistance drops slower than voltage on bitlines reading PCM cellswith low resistance. Thus, the time for a bitline to discharge fromV_(pre) to V_(thr) is representative of the resistance (and logicalstate, if applicable) stored by a PCM cell being read by that bitline.

The time needed for a bitline to discharge from V_(pre) (prechargevoltage) to v_(thr) (sensing threshold voltage) is found by reworkingEquation 1 to solve for time t in terms of resistance R, andsubstituting

$\frac{vthr}{vpre}$

for V(t).

$\begin{matrix}{t = {{- {RC}}\mspace{11mu} {\ln \left( {1 - \frac{vthr}{vpre}} \right)}}} & {{Equation}\mspace{14mu} 2}\end{matrix}$

The PCM cell resistance is translated into a signal switch latency bythe sense amplifier, which is triggered to change its output state(generate an output) when the bitline voltage drops to the sensethreshold voltage. That timing is carried through to timing units (e.g.,latches). Timing units latch binary outputs when sense amplifieroutputs, corresponding to PCM cells with particular resistances,transition at the timing units. This is essentially a comparison betweenthe discharge times for respective bitlines reading corresponding PCMcells (generally, transmission time is relatively small).

A timing unit can, for example, latch on the first of multiple senseamplifier outputs transitioning at the timing unit. Of the PCM cellswith read outputs causing the sense amplifier outputs that areconfigured to be received by the timing unit, the sense amplifier outputtriggering the timing unit to latch corresponds to the PCM cell with thelowest resistance.

In some embodiments, a sense amplifier output corresponding to a PCMcell storing data (PCM data cell) can be compared to a sense amplifieroutput corresponding to a PCM cell storing a reference (PCM referencecell). A reference comprises a boundary, or switchover point,discriminating between PCM data cell resistances corresponding toadjacent logical states as stored in a PCM cell. A reference candiscriminate between such resistances using state change (senseamplifier output) timing information.

A reference can be chosen to be a resistance between the resistancescorresponding to a pair of adjacent logical states to be discriminatedby the reference. This means a sense amplifier output corresponding to aPCM reference cell will transition at a timing unit between senseamplifier outputs corresponding to the logical states discriminated bythe reference.

Discrimination by a reference between a pair of adjacent logical statesalso comprises discriminating between logical states corresponding toPCM cell resistances lower than the reference resistance, and logicalstates corresponding to PCM cell resistances higher than the referenceresistance (with a margin of error related to factors which can include,e.g., data path component response times, data path transmission time,and variation of reference resistance as written from intended referenceresistance).

FIG. 1A schematically shows an example of a PCM memory, and specificallya read path for single-ended sensing of single-bit PCM cells. Afterprecharge, bitlines where the accessed PCM cell is in a low-resistancestate (e.g. a “Set” state) will change voltage faster than bitlinesconnected to a high-resistance state (“Reset” state). The sense ampconnected to each bitline will preferably transition once the bitlinevoltage crosses a certain level, so the sense amp's output DOUT willtransition sooner for bitlines where the accessed cell is in thelow-resistance state. Since the reference PCM cells are designed topresent an intermediate resistance, the sense amps connected to thereference PCM cells will transition after those connected tolow-resistance PCM cells, but before those connected to high-resistancePCM cells.

In this example, a 3-to-1 Vote unit 16 drives line CLK0 active as soonas a majority (two) of the sense amplifier reference outputs 14transition at the 3-to-1 Vote Unit 16. When CLK0 goes active, latches 20will each latch a respective sense amplifier output DOUT onto a dataline DAT. If the respective DOUT line has already transitioned at thattime, the transitioned state will be latched onto the DAT line,indicating a SET cell. If the respective DOUT line has not yettransitioned when CLK0 transitions, the untransitioned state will belatched onto the DAT line, indicating a RESET cell. Note that the senseamp outputs DOUT for RESET cells will transition eventually, but, onceCLK0 has activated the latches, the state of the DOUT lines isirrelevant. Note that the logic in latches 20 can make a SET statecorrespond to a logic “0” or a logic “1”, whichever is desired.

When a group of PCM cells (a number of PCM cells configured to be readtogether, e.g., a word) is accessed to be read, corresponding bitlines 2are precharged to a precharge voltage.

In this example multiplexers 4 (MUX) are used to select from a group ofbitlines 10 the corresponding bitline 2 carrying the read output of aPCM cell being read, and direct that read output to a correspondingsense amplifier 6. In FIG. 1A, sense amplifiers 6 and write heads 8(used during PCM cell write accesses) are part of combined SA/WH units10 (sense amplifier/write head units 10). SA/WH units 10 are severallyattached to respective groups of bitlines 2 (e.g., 64 bitlines per SA/WHunit 10) and multiplexers 4 (generally, one per SH/WH unit 10). (FIG. 1Ashows all of this only for one example SA/WH unit 10. This is due todrawing shorthand, and does not reflect or imply absence incorresponding embodiments.)

Once the corresponding bitlines 2 are precharged, the voltage clamp isremoved and they are allowed to discharge. When a bitline 2 hasdischarged to a sense threshold voltage, its corresponding senseamplifier output 12 will transition. The time from voltage clamp removalto sense amplifier output transition is determined by the resistance ofthe corresponding bitline 2, assuming the capacitances of the bitlines 2are nearly equal. Typically, the bitline resistance is predominantly theresistance of the PCM cell being read using that bitline 2. (There canbe a small process-dependent leakage current also.)

Three of the PCM cells being read (with sense amplifier outputs 12connected to a 3-to-1 Vote unit 16) contain a reference resistance (PCMreference cells), and the rest of the PCM cells being read contain data(PCM data cells). PCM reference cell read outputs result incorresponding sense amplifiers 6 outputting sense amplifier referenceoutputs 14. Once a majority of the PCM reference cell read outputs(here, two out of three) cause corresponding sense amplifier referenceoutputs 14 to be outputted, and the sense amplifier reference outputs 14transition at the 3-to-1 Vote unit 16, the 3-to-1 Vote unit 16 outputsCLK0 18 (a clock signal). CLK0 18 is used as a reference with respect tosense amplifier outputs 12. LATCH units 20 latch and output differentbinary data outputs 22 depending on whether CLK0 18 or a sense amplifieroutput 12 (corresponding to a PCM data cell being read) is outputted andtransitions at the LATCH unit 20 first. Binary data outputs 22 generallycorrespond to the binary values originally written to corresponding PCMdata cells.

The signal transitioning at the LATCH unit 20 first does so as a resultof shorter discharge time(s), starting at (approximately) the prechargevoltage at voltage clamp release, and ending at the sense thresholdvoltage. Shorter time(s) result from lower resistance(s) of the PCMcell(s) being read, while longer time(s) result from higherresistance(s) of the PCM cell(s) being read.

Actual resistances of PCM cells as written vary somewhat from intendedresistances. This results in variation in sense amplifier output 12timings during read accesses. Use of the 3-to-1 Vote unit 16 reduces thelikelihood of outlier values for CLK0 18 output timing (and generallyreduces probable variation in CLK0 18 output timing), since the senseamplifier reference output 14 with the median timing triggers CLK0 18output. This results in a more reliable time-based reference. A morereliable reference means a greater effective sense margin, and thus morereliable PCM reads.

FIG. 1B shows an example of a timing diagram for single-bit (2-level)time-based decoding PCM memory reads. There is some variation in thetiming of state changes as shown in timing figures (FIGS. 1B, 4B and6B), because resistances of PCM cells as written typically vary fromintended resistances.

As shown in FIG. 1B, a clock signal CLK0 64 transitions (at time 66)once a majority of sense amplifier reference outputs Ref-A (labeled as14 or 58) have transitioned (in the time period 60). If a senseamplifier output 12 transitions before CLK0 transitions, then itcorresponds to a data cell with a lower resistance than the referencecells—i.e., an output like Set Data 50 output. In this case, acorresponding binary output Set Data DAT 56 can be latched 54 atapproximately the time of Set Data Dout 50 output 52.

If the sense amplifier output 12 is outputted after CLK0 64, then it isa sense amplifier output 12 corresponding to a data cell with a higherresistance than the reference cells—i.e., a Reset Data Dout 76 output78. In this case, a corresponding binary output Reset Data DAT 70 can belatched 68 at approximately the time of CLK0 64 output 66.

Once CLK0 64 is output 66, a Read Done 72 signal can be outputted 74.Embodiments as shown in FIG. 1B can realize a read cycle speed advantagebecause it is unnecessary to wait for Reset Data Dout 76 output 78 toproduce PCM memory outputs.

In embodiments corresponding to FIG. 1B, Set Data Dout 50 corresponds tosense amplifier outputs 12 of PCM cells written with Set, which are thefirst sense amplifier outputs 12 to change state 52 (sense amplifiersoutput when sense amplifier outputs change state). Once Set Data Dout 50changes state 52, the state change 52 is propagated to correspondingtiming units (e.g., LATCH units 20) and causes them to change state 54,outputting binary data output 22 SET Data DAT 56. A Set Data DAT 56output indicates that a corresponding PCM cell is storing a Set state.

Three PCM reference cells storing the same reference correspond to senseamplifier reference outputs 14 Ref-A 58. PCM reference cellscorresponding to Ref-A have higher resistance than PCM data cellsstoring Set, and lower resistance than PCM data cells storing Reset.Ref-A 58 change state 60 (are outputted by sense amplifiers 6) after SetData Dout 50. When a majority of the Ref-A 58 sense amplifier referenceoutputs 14 change state 60, and the majority-making Ref-A 58 statechange 60 is propagated to and received by 62 a 3-to-1 Vote unit 16, aclock signal CLK0 64 changes state 66. Timing units (e.g., LATCH units20) to which a CLK0 64 state change 66 is propagated first—before asense amplifier output 12 state change-change state 68, outputtingbinary output 22 Reset Data DAT 70. A Reset Data DAT 70 output indicatesthat a corresponding PCM cell is storing a Reset state.

Once CLK0 64 changes state 66, it causes a Read Done 72 to change state74, indicating that the PCM cell decoding is complete. Total read timecan be shortened by not waiting for Reset Data Dout 76 to change state78 before outputting Read Done 72.

FIG. 1C shows an example of gate logic for a 3-to-1 Vote unit. Forinputs A, B and C, this gate logic determines the Boolean result(AB+AC+BC). Any pair of two TRUE inputs will produce a TRUE output.

Three initial NAND logic gates 100 each take a different pair of inputs102 chosen from three total inputs. Inputs correspond to sense amplifierreference outputs 14. The outputs of the three initial NAND logic gates104 are input into a fourth NAND logic gate 106. The output of thefourth NAND logic gate 108 corresponds to CLK0 signal 18, 64.

FIG. 3 schematically shows an example of a 3-level multibit PCMtime-based single-ended decoding configuration. Bitline 2 and senseamplifier 6 functions are similar to those in embodiments as shown inFIG. 1A. Here, two different references (corresponding to two differentsets of three reference cells each) and two 3-to-1 Vote units 304, 306are used to produce two different clock signals CLK0 308 and CLK1 310 inorder to discriminate between the two different pairs of adjacent3-level logical states. Individual sense amplifier outputs 12corresponding to data cells are received by two different LATCH units300, 302. LATCH units 300 also receive CLK0 308, while LATCH units 302receive CLK1 310. Sense amplifier outputs 12 can transition atcorresponding LATCH units 300, 302 before, between or after clocksignals CLK0 308 and CLK1 310. The resulting two bits of binary output312 from a pair of LATCH units 300, 302 corresponding to a data cellthus indicate whether the data cell stores a resistance lower than,between, or higher than the two different resistances of the twodifferent references.

In embodiments corresponding to FIG. 3, individual sense amplifieroutputs 12 corresponding to individual PCM data cell read outputs areconfigured to be received by two LATCH units 300, 302 (rather than oneLATCH unit 20, as in FIG. 1A).

Two 3-to-1 Vote units 304, 306 generate two different clock signals,respectively CLK0 308 and CLK 1 310. 3-to-1 Vote units 304, 306respectively output clock signals CLK0 308 and CLK1 310 when a majorityof their respective sense amplifier reference outputs 14 transition atthe 3-to-1 Vote units 304, 306. 3-to-1 Vote units 304, 306 can, forexample, use the logic gate arrangement shown in FIG. 1C.

CLK0 308 and CLK1 310 are each based on one of two different references,and discriminate correspondingly different pairs of adjacent logicalstates. For example, references can be chosen such that times t(R) (timet as a function of resistance R) from voltage clamp release to senseamplifier output state change, for resistances corresponding to variousPCM states (logical states) and clock signals, obey the followinginequality: t(lowest R PCM state)<t(CLK0 320)<t(middle R PCMstate)<t(CLK1 325)<t(highest R PCM state).

CLK0 308 is configured to be received by different ones of the pair ofLATCH units 300, 302 corresponding to individual PCM data cells thanCLK1 310. LATCH units 300, 302 produce different binary outputs 312depending on whether a sense amplifier output 12 or a clock signal (CLK0308 or CLK1 310, respectively) transitions first.

Three LATCH units 300 are configured to receive sense amplifierreference outputs 14 corresponding to one of the two references, as wellas a clock signal CLK0 308 corresponding to the other reference. Thebinary outputs 312 of these three LATCH units 300 can serve as a checkthat PCM reference cells are being written and read properly.

FIG. 4A shows an example of a 4-level multibit PCM single-ended decodingconfiguration. Bitline 2 and sense amplifier 6 functions are similar tothose in embodiments as shown in FIG. 1A. Here, three differentreferences (corresponding to two different sets of three referencecells) and three 3-to-1 Vote units 406, 408, 410 are used to producethree different clock signals CLK0 412, CLK 1 414 and CLK2 416 in orderto discriminate between the three different pairs of adjacent logicalstates in 4-level multibit PCM.

Individual sense amplifier outputs 12 corresponding to data cells arereceived by three different LATCH units 400, 402 and 404. LATCH units400 receive CLK0 412, while LATCH units 402 receive CLK1 414 and LATCHunits 404 receive CLK2 416. Sense amplifier outputs 12 can transition atcorresponding LATCH units 400, 402, 404 before, between an adjacent pairof, or after clock signals CLK0 412, CLK1 414, and CLK2 416. Theresulting three bits of encoded binary output 418 from a triple of LATCHunits 400, 402, 404 corresponding to a data cell indicate whether thedata cell stores a resistance lower than, between a pair of, or higherthan the three different resistances of the three different references.Encoded binary output 418 triples are decoded by corresponding 4-LevelDecoders 420 to produce decoded binary data outputs 422. Decoded binarydata outputs 422 can be, for example, the binary values written tocorresponding data cells, or values contained in the read instructionthat caused the data cells to be written.

In some sample embodiments corresponding to FIG. 4A, individual senseamplifier outputs 12 corresponding to individual PCM data cell readoutputs are configured to be received by three LATCH units 400, 402,404.

Three 3-to-1 Vote units 406, 408, 410 generate three different clocksignals, respectively CLK0 412, CLK 1 414, and CLK2 416. When a majorityof respective sense amplifier reference outputs 14 transitions at a3-to-1 Vote unit it outputs its respective clock signal CLK0 412, CLK1414 or CLK2 416. 3-to-1 Vote units 406, 408 and 410 can, for example,use the logic gate arrangement shown in FIG. 1C.

CLK0 412, CLK1 414 and CLK2 416 are each based on one of three differentreferences, and discriminate, correspondingly, between different pairsof adjacent logical states. For example, references can be chosen suchthat times t(R) (time t as a function of resistance R) from voltageclamp release to sense amplifier output state change, for resistancescorresponding to various PCM states (logical states) and clock signals,obey the following inequality: t(lowest R PCM state)<t(CLK0 412)<t(lowermiddle R PCM state)<t(CLK1 414)<t(upper middle R PCM state)<t(CLK2416)<t(highest R PCM state).

CLK0 412, CLK1 414 and CLK2 416 are each configured to be received bydifferent ones of the three LATCH units 400, 402, 404 corresponding toindividual PCM data cells. A LATCH unit 400, 402 or 404 producesdifferent encoded binary outputs 418 depending on whether a senseamplifier output 12 or a clock signal (CLK0 412, CLK1 414 or CLK2 416,respectively) received by the LATCH unit 400, 402 or 404 transitionsfirst.

Encoded binary outputs 418 from LATCH units 400, 402, 404 are decoded by4-Level Decoders 420. Resulting decoded binary data outputs 422 cancorrespond to, for example, logical states with which corresponding PCMdata cells were written, or to binary data as received by the PCM memoryin one or more write requests that caused corresponding PCM cells to bewritten.

Three 3-to-1 Vote units 424, 426, 428 are configured to receive outputsof various LATCH units 400, 402 that variously receive sense amplifierreference outputs 14 corresponding to two of the three references (thereferences corresponding to CLK1 414 and CLK2 416), and are variouslyclocked by clock signals CLK0 412 and CLK1 414. Inputs to the 3-to-1Vote units 424, 426, 428 are arranged so that there is an expectedtime-ordering to their outputs. The outputs of the 3-to-1 Vote units424, 426, 428 are decoded by a 4-Level Decoder 430, which producesbinary outputs 432 that indicate whether PCM reference cells are beingwritten and read properly.

FIG. 4B shows an example of a timing diagram for 4-level multibit PCMtime-based single-ended decoding.

As shown in FIG. 4B, clock signals CLK0 1408, CLK1 1416 and CLK2 1424are outputted 1410, 1418, 1426 once a majority (two) of sense amplifierreference outputs 14, 1412, 1420, 1428 corresponding to the respectivedifferent references are outputted 1414, 1422, 1430. If a senseamplifier output 12 is outputted before CLK0 1408, then it is a senseamplifier output 12 corresponding to a data cell with a lower resistancethan the reference cells—i.e., “00” Data Dout 1400 output 1436. Acorresponding binary output “00” Data DAT 1432 can be latched 1434 atapproximately the time of “00” Data Dout 1400 output 1436. (Typically,transmission time from sense amplifiers to corresponding timing units isrelatively short.)

If the sense amplifier output 12 is outputted between CLK0 1408 and CLK11416, then it is a sense amplifier output 12 corresponding to a datacell with a resistance between the references corresponding to CLK0 1408and CLK1 1416—i.e., a “01” Data Dout 1402 output 1442. A correspondingbinary output “01” Data DAT 1438 can be latched 1440 at approximatelythe time of CLK1 1416 output 1418.

If the sense amplifier output 12 is outputted between CLK1 1416 and CLK21424, then it is a sense amplifier output 12 corresponding to a datacell with a resistance between the references corresponding to CLK1 1416and CLK2 1424—i.e., a “10” Data Dout 1404 output 1448. A correspondingbinary output “10” Data DAT 1444 can be latched 1446 at approximatelythe time of CLK2 1424 output 1426.

If the sense amplifier output 12 is outputted after CLK2 1424, then itis a sense amplifier output 12 corresponding to a data cell with aresistance higher than the references corresponding to CLK2 1424—i.e., a“11” Data Dout 1406 output 1458. A corresponding binary output “11” DataDAT 1450 can be latched 1452 at approximately the time of CLK2 1424output 1426.

Once CLK2 1424 is output 1426, a Read Done 1452 signal can be outputted1454. Embodiments as shown in FIG. 4B can realize a read cycle speedadvantage because it is unnecessary to wait for “11” Data Dout 1406output 1458 to produce PCM memory outputs (e.g., by decoding the variousbinary outputs).

As shown in FIG. 4B, sense amplifier outputs 12 “00” Data Dout 1400,“01” Data Dout 1402, “10” Data Dout 1404, and “11” Data Dout 1406respectively correspond to PCM cells storing “00”, “01”, “10” and “11”logical states. In embodiments as shown in FIG. 4B, “00” is thelowest-resistance state.

CLK0 1408 changes state 1410 after a majority of sense amplifierreference outputs 14 Ref-B 1412 change state 1414, and the state changes1414 are propagated to a corresponding Vote unit. Ref-B 1412 correspondsto the lowest-resistance reference.

CLK1 1416 changes state 1418 after a majority of sense amplifierreference outputs 14 Ref-A 1420 change state 1422, and the state changes1422 are propagated to a corresponding Vote unit. Ref-A 1420 correspondsto the middle-resistance reference.

CLK2 1424 changes state 1426 when a majority of sense amplifierreference outputs 14 Ref-C 1428 change state 1430, and the state changes1430 are propagated to a corresponding Vote unit. Ref-C corresponds tothe highest-resistance reference.

“00” Data DAT 1432 changes state 1434, outputting decoded binary data422, after “00” Data Dout 1400 changes state 1436, the state change 1436is propagated to corresponding timing units, and resulting timing unitoutputs are propagated to corresponding 4-level decoders.

“01” Data DAT 1438 changes state 1440, outputting decoded binary data422, after “01” Data Dout 1402 changes state 1442; CLK0 1408 changesstate 1410; CLK1 1416 changes state 1418; state changes 1410, 1418, 1442are propagated to corresponding timing units; and resulting timing unitoutputs are propagated to corresponding 4-level decoders.

“10” Data DAT 1444 changes state 1446, outputting decoded binary data422, after “10” Data Dout 1404 changes state 1448; CLK0 1408 changesstate 1410; CLK1 1416 changes state 1418; CLK2 1424 changes state 1426;state changes 1410, 1418, 1424, 1448 are propagated to correspondingtiming units; and resulting timing unit outputs are propagated tocorresponding 4-level decoders.

“11” Data DAT 1450 changes state 1452, outputting decoded binary data422, after CLK0 1408 changes state 1410; CLK1 1416 changes state 1418;CLK2 1424 changes state 1426; state changes 1410, 1418, 1424 arepropagated to corresponding timing units; and resulting timing unitoutputs are propagated to corresponding 4-level decoders.

Once CLK2 1424 changes state 1426, it causes a Read Done 1454 to changestate 1456, indicating that the PCM cell decoding is complete. Totalread time can be shortened by not waiting for “11” Data Dout 1406 tochange state 1458 before outputting Read Done 1456.

FIG. 5 shows an example of a single-bit (2-level) PCM time-baseddifferential decoding configuration. Pairs of sense amplifier outputs 12received by individual LATCH units 500 correspond to pairs of PCM datacells storing complementary pairs of logical states, i.e., one Set stateand one Reset state per pair of PCM data cells. Individual LATCH units500 output binary outputs 502 based on which of the correspondingcomplementary pair of sense amplifier outputs 12 transitions first atthe LATCH unit 500.

FIG. 6A shows an example of a 4-level multibit PCM time-baseddifferential decoding configuration. In some sample embodiments, 4-LevelDecoders 600 receive groups of four sense amplifier outputs 12corresponding to groups of four 4-level multibit PCM data cells. Thereare six possible pairs of the four sense amplifier outputs 12corresponding to a group of cells. Within a 4-Level Decoder 600, the sixpossible pairs are received by six corresponding LATCH units 602,resulting in 24 (4!) possible collective states for the six LATCH unitoutputs 604 (corresponding to the 24 possible collective states for thegroup of cells). A LATCH unit output 604 is determined by which of apair of sense amplifier outputs 12 received by the LATCH unit 602transitions at the LATCH unit 602 first.

The six LATCH unit outputs 604 are decoded by a 24-State Decoder 606.The 24-State Decoder 606 generates, and the 4-Level Decoder 600 outputs,resulting binary data outputs 608 corresponding to the collective statesencoded by four-cell groups of 4-level PCM data cells.

FIG. 6B shows an example of a timing diagram for 4-level multibit PCMtime-based differential decoding. Each sense amplifier output 12 DOUT650 in a four-cell group of 4-level multibit PCM stores a differentresistance level corresponding to a different logical state 652. Sixtiming units compare each different pair of DOUT 650. A timing unitoutput 654 changes state 656 depending on which of a pair of data cells,corresponding to the pair of DOUT 650 received by the timing unit, hasthe lower resistance—i.e., which of the pair of DOUT 650 received by thetiming unit changes state 658 and transitions at the timing unit first.Once the six timing units have changed state 656, the sensing process iscomplete and a valid data signal is outputted 660.

The six timing units will change state 656 once three of the DOUT 650 ina corresponding four-cell group have changed state 658. Not having towait for the fourth cell to change state 658 allows embodimentscorresponding to FIG. 6B to realize read cycle speed gains.

FIG. 7 shows an example of a processing system 700. Power control 702manages distribution of power from a power source 704 to othercomponents of the processing system. A processing unit 706 (e.g., aprocessor) performs processing functions, and an I/O control 708(input/output) operates and manages communications with, and enablesother processing system components 702, 706, 708, 712 to operate andmanage communications with, external devices 710 and other externalelements. The power control 702, processing unit 706 and I/O control 708can also make memory access calls to a memory 712. Memory 712 can be aPCM memory, and/or can contain an embedded PCM memory. Processing systemcomponents 702, 706, 708, 712 perform their functions based onconfiguration data stored by nonvolatile PCM memory integrated intorespective processing system components 702, 706, 708, 712.

According to some but not necessarily all embodiments, there isprovided: A method of operating a phase-change memory, comprising:precharging data and reference bitlines, and accessing respectivephase-change memory cells which shunt corresponding ones of said databitlines, while a reference cell shunts said reference bitline; usingrespective sense amplifiers for said bitlines, each outputting a logictransition when the corresponding bitline reaches a sense thresholdvoltage; wherein said reference bitline always reaches said sensethreshold voltage more slowly than data bitlines where said memory cellsare in the lowest-resistance one of their possible data-dependentstates; multiple sense amplifiers, each connected to at least arespective one of said bitlines, and each configured to output a logictransition when the voltage of the bitline passes a fixed thresholdvoltage; and latching circuits, jointly clocked by the output of a senseamplifier connected to said reference bitline, and which arerespectively connected to receive and latch respective outputs of saidsense amplifiers; whereby sensing occurs without requiring said senseamplifiers to reach a stable state.

According to some but not necessarily all embodiments, there isprovided: A phase-change memory, comprising: multiple phase-changememory cells, each having a higher or lower resistance; multiple databitlines, each connected to be shunted by a selected one of said datacells, and at least one reference bitline, connected to be shunted by areference cell; wherein said reference cell discharges said referencebitline with a time constant which is slower than the time constant ofsaid lower resistance in discharging said data bitlines; multiple senseamplifiers, each connected to at least a respective one of saidbitlines, and each configured to output a logic transition when thevoltage of the bitline passes a fixed threshold voltage; and latchingcircuits operatively connected to receive respective outputs of saidsense amplifiers; wherein a respective one of said sense amplifiers isconnected to said reference bitline, and provides an output which isconnected to activate said latching circuits; whereby sensing occurswithout requiring said sense amplifiers to reach a stable state.

According to some but not necessarily all embodiments, there isprovided: A phase-change memory, comprising: multiple phase-changememory cells, each having either a higher-resistance state or alower-resistance state, depending on what data has been saved into thephase-change memory cells; multiple data bitlines, each connected to beshunted by a selected one of said cells, and at least one referencebitline, connected to be shunted by a reference cell; wherein the ratioof current passed by said reference cell to the capacitance of saidreference bitline is smaller than the ratio of current passed by ones ofsaid cells which are in said lower-resistance state to the capacitanceof said data bitline; precharge circuitry which applies a prechargevoltage to some or all of said bitlines; multiple sense amplifiers, eachconnected to at least a respective one of said bitlines, and eachconfigured to output a logic transition when the voltage of the bitlinepasses a fixed threshold voltage; and latching circuits operativelyconnected to receive respective outputs of said sense amplifiers;wherein a respective one of said sense amplifiers is connected to saidreference bitline, and provides an output which is connected to activatesaid latching circuits; whereby sensing occurs without requiring saidsense amplifiers to reach a stable state.

According to some but not necessarily all embodiments, there isprovided: a memory, comprising: multiple groups of phase change memorycells, ones of said groups comprising multiple phase change memorystorage cells and multiple phase change memory reference cells storingone or more references, and configured such that said storage cells andsaid reference cells in ones of said groups are read together; multiplesense amplifiers, ones of said sense amplifiers configured to sense readoutputs of corresponding ones of said storage cells and said referencecells when one of said groups is read, and to produce sense amplifieroutputs at times at least partially dependent on the states stored bysaid corresponding storage cells and reference cells; one or more voteunits, ones of said vote units configured to generate a clock signalwhen a majority of said sense amplifier outputs corresponding to one ofsaid references are detected to have transitioned at said vote unit; andmultiple output units, ones of said output units configured to output adifferent binary value depending on whether one of said clock signals orone of said sense amplifier outputs corresponding to one of said storagecells changes state first at said output unit.

According to some but not necessarily all embodiments, there isprovided: a memory, comprising: multiple groups of phase change memorycells, ones of said groups comprising multiple phase change memorystorage cells and multiple phase change memory reference cells storingone or more references, and configured such that said storage cells andsaid reference cells in ones of said groups are read together; multiplesense amplifiers, ones of said sense amplifiers configured to sense readoutputs of corresponding ones of said storage cells and said referencecells when one of said groups is read, and to produce sense amplifieroutputs at times at least partially dependent on the states stored bysaid corresponding storage cells and reference cells; and multipleoutput units, ones of said output units configured to output a differentbinary value depending on whether a reference signal generated in atleast partial dependence on one or more of said sense amplifier outputscorresponding to one of said references, or one of said sense amplifieroutputs corresponding to one of said storage cells, first change stateat said output unit.

According to some but not necessarily all embodiments, there isprovided: a memory, comprising: multiple groups of phase change memorycells, ones of said groups comprising multiple groups of at least twophase change memory storage cells, said groups configured such that saidstorage cells in ones of said groups are read together, cells in ones ofsaid groups of cells configured to store different logical states thatare unique within said group of cells to define a collective state ofsaid group of cells; multiple sense amplifiers, ones of said senseamplifiers configured to sense read outputs of corresponding ones ofsaid storage cells when one of said groups is read, and to produce senseamplifier outputs at times at least partially dependent on the statesstored by said corresponding storage cells; and multiple output units,ones of said output units configured to output a different binary valuedepending on which of a pair of said sense amplifier outputscorresponding to cells in one of said groups of cells first change stateat said output unit.

According to some but not necessarily all embodiments, there isprovided: a memory, comprising: multiple bitlines configured to readmultiple selected ones of multiple phase change memory cells byprecharging to approximately a precharge voltage and then discharging toa sense threshold voltage; multiple sense amplifiers configured tooutput when ones of said sense amplifiers detect that corresponding onesof said bitlines have discharged to said sense threshold voltage; one ormore vote units, ones of said vote units configured to generate a clocksignal on detection of transition at said vote unit of a majority ofsense amplifier outputs corresponding to one of one or more referencesstored in multiple ones of said phase change memory cells; and multipleoutput units configured to output binary values depending on the orderin which said clock signal, and a sense amplifier output correspondingto a phase change memory cell storing data, change state atcorresponding ones of said output units.

According to some but not necessarily all embodiments, there isprovided: a memory, comprising: multiple bitlines configured to readmultiple selected ones of multiple phase change memory cells byprecharging to approximately a precharge voltage and then discharging toa sense threshold voltage; multiple sense amplifiers configured tooutput when ones of said sense amplifiers detect that corresponding onesof said bitlines have discharged to said sense threshold voltage; andmultiple output units configured to output binary values depending onthe order in which sense amplifier outputs change state at correspondingones of said output units.

According to some but not necessarily all embodiments, there isprovided: a method of operating a memory, comprising: prechargingmultiple bitlines configured to enable read access to multiple phasechange memory cells, and read accessing said cells using said bitlines;discharging said bitlines when charged to approximately a prechargevoltage; sending sense amplifier outputs to corresponding ones ofmultiple output units when ones of multiple sense amplifiers detect thatcorresponding ones of said bitlines have discharged to a sense thresholdvoltage; generating one or more clock signals when ones of one or morevote units detect transition at said vote unit of a majority of senseamplifier outputs corresponding to ones of one or more references storedin multiple ones of said phase change memory cells; and outputtingbinary values depending on the order in which said clock signal, andones of said sense amplifier outputs corresponding to ones of said phasechange memory cells storing data, change state at corresponding ones ofsaid output units.

According to some but not necessarily all embodiments, there isprovided: a method of operating a memory, comprising: prechargingmultiple bitlines configured to enable read access to multiple phasechange memory cells, and read accessing said cells using said bitlines;discharging said bitlines when charged to approximately a prechargevoltage; when ones of multiple sense amplifiers detect thatcorresponding ones of said bitlines have discharged to a sense thresholdvoltage, sending sense amplifier outputs to corresponding ones ofmultiple output units; and outputting binary values depending on theorder in which two or more of said sense amplifier outputs change stateat corresponding ones of said output units.

According to some but not necessarily all embodiments, there isprovided: a method of operating a memory, comprising: reading togethermultiple phase change memory storage cells and multiple phase changememory reference cells storing one or more references; sensing readoutputs of said storage cells and said reference cells using multiplecorresponding sense amplifiers; generating sense amplifier outputs attimes at least partially dependent on the states stored by said storagecells and said reference cells; generating one or more clock signals,ones of said clock signals being generated when a majority of said senseamplifier outputs corresponding to one of said references are detectedto have transitioned at a corresponding one of one or more vote units;and outputting binary values, ones of said binary values depending onwhether one of said clock signals or one of said sense amplifier outputscorresponding to one of said storage cells is first to change state atone of multiple output units.

According to some but not necessarily all embodiments, there isprovided: a method of operating a memory, comprising: reading togethermultiple phase change memory storage cells and multiple phase changememory reference cells storing one or more references; sensing readoutputs of said storage cells and said reference cells using multiplecorresponding sense amplifiers; generating sense amplifier outputs attimes at least partially dependent on the states stored by said storagecells and said reference cells; and outputting binary values, ones ofsaid binary values depending on whether a reference signal generated inat least partial dependence on one or more of said sense amplifieroutputs corresponding to one of said references, or one of said senseamplifier outputs corresponding to one of said storage cells, is firstto change state at one of multiple output units.

According to some but not necessarily all embodiments, there isprovided: a memory, comprising: reading together multiple groups of atleast two phase change memory storage cells, cells in ones of saidgroups of cells configured to store different logical states that areunique within said group of cells to define a collective state of saidgroup of cells; sensing read outputs of said storage cells usingmultiple corresponding sense amplifiers; generating sense amplifieroutputs at times at least partially dependent on the states stored bysaid storage cells and said reference cells; and outputting binaryvalues, ones of said binary values depending on which of a pair of saidsense amplifier outputs corresponding to cells in one of said groups ofcells first changes state at ones of multiple output units.

According to some but not necessarily all embodiments, there isprovided: a processing system, comprising: one or more memory units, oneor more processors which execute programmable instruction sequences, andone or more input/output units; a phase change memory unit; multiplegroups of phase change memory cells within said phase change memory unitconfigured to store and output configuration data, ones of said groupscomprising multiple phase change memory storage cells and multiple phasechange memory reference cells storing one or more references, andconfigured such that said storage cells and said reference cells in onesof said groups are read together; multiple sense amplifiers, ones ofsaid sense amplifiers configured to sense read outputs of correspondingones of said storage cells and said reference cells when one of saidgroups is read, and to produce sense amplifier outputs at times at leastpartially dependent on the states stored by said corresponding storagecells and reference cells; one or more vote units, ones of said voteunits configured to generate a clock signal when a majority of saidsense amplifier outputs corresponding to one of said references aredetected to have transitioned at said vote unit; and multiple outputunits, ones of said output units configured to output a different binaryvalue depending on whether one of said clock signals or one of saidsense amplifier outputs corresponding to one of said storage cells firstchanges state at said output unit; wherein said processor and/or saidinput/output unit are configured to operate external elements inaccordance with said configuration data.

According to some but not necessarily all embodiments, there isprovided: a processing system, comprising: one or more memory units, oneor more processors which execute programmable instruction sequences, andone or more input/output units; a phase change memory unit; multiplegroups of phase change memory cells within said phase change memory unitconfigured to store and output configuration data, ones of said groupscomprising multiple phase change memory storage cells and multiple phasechange memory reference cells storing one or more references, andconfigured such that said storage cells and said reference cells in onesof said groups are read together; multiple sense amplifiers, ones ofsaid sense amplifiers configured to sense read outputs of correspondingones of said storage cells and said reference cells when one of saidgroups is read, and to produce sense amplifier outputs at times at leastpartially dependent on the states stored by said corresponding storagecells and reference cells; and multiple output units, ones of saidoutput units configured to output a different binary value depending onwhether a reference signal generated in at least partial dependence onone or more of said sense amplifier outputs corresponding to one of saidreferences, or one of said sense amplifier outputs corresponding to oneof said storage cells, first changes state at said output unit; whereinsaid processor and/or said input/output unit are configured to operateexternal elements in accordance with said configuration data.

According to some but not necessarily all embodiments, there isprovided: a processing system, comprising: one or more memory units, oneor more processors which execute programmable instruction sequences, andone or more input/output units; a phase change memory unit; multiplegroups of phase change memory cells within said phase change memory unitconfigured to store and output configuration data, ones of said groupscomprising multiple groups of at least two phase change memory storagecells, said groups configured such that said storage cells in ones ofsaid groups are read together, cells in ones of said groups of cellsconfigured to store different logical states that are unique within saidgroup of cells to define a collective state of said group of cells;multiple sense amplifiers, ones of said sense amplifiers configured tosense read outputs of corresponding ones of said storage cells when oneof said groups is read, and to produce sense amplifier outputs at timesat least partially dependent on the states stored by said correspondingstorage cells; multiple output units, ones of said output unitsconfigured to output a different binary value depending on which of apair of said sense amplifier outputs corresponding to cells in one ofsaid groups of cells first changes state at said output unit; andwherein said processor and/or said input/output unit are configured tooperate external elements in accordance with said configuration data.

According to some but not necessarily all embodiments, there isprovided: a method of operating a processing system comprising a phasechange memory unit, a processor which executes programmable instructionsequences, and an input/output unit, comprising: precharging multiplebitlines configured to enable read access to multiple phase changememory cells, and read accessing said cells using said bitlines, saidphase change memory cells being configured to store configuration data;discharging said bitlines when charged to approximately a prechargevoltage; sending sense amplifier outputs to corresponding ones ofmultiple output units when ones of multiple sense amplifiers detect thatcorresponding ones of said bitlines have discharged to a sense thresholdvoltage; generating a clock signal when ones of one or more vote unitsdetect transition at said vote unit of a majority of sense amplifieroutputs corresponding to ones of one or more references stored inmultiple ones of said phase change memory cells; outputting binaryvalues depending on the order in which said clock signal, and ones ofsaid sense amplifier outputs corresponding to phase change memory cellsstoring data, first change state at corresponding ones of said outputunits; and operating external elements using said processor and/or saidinput/output unit in accordance with said configuration data.

According to some but not necessarily all embodiments, there isprovided: a method of operating a processing system comprising a phasechange memory unit, a processor which executes programmable instructionsequences, and an input/output unit, comprising: precharging multiplebitlines configured to enable read access to multiple phase changememory cells, and read accessing said cells using said bitlines, saidphase change memory cells being configured to store configuration data;discharging said bitlines when charged to approximately a prechargevoltage; when ones of multiple sense amplifiers detect thatcorresponding ones of said bitlines have discharged to a sense thresholdvoltage, sending sense amplifier outputs to corresponding ones ofmultiple output units; outputting binary values depending on the orderin which two or more of said sense amplifier outputs change state atcorresponding ones of said output units; and operating external elementsusing said processor and/or said input/output unit in accordance withsaid configuration data.

According to some but not necessarily all embodiments, there isprovided: methods and systems for time-based cell decoding for PCMmemory. Generally, the higher the PCM element resistance, the longer ittakes for a read output to change state. PCM memory output is determinedusing differentiated timings of read outputs changing state, rather thandifferentiated values of read outputs. In some single-bitsingle-ended-sensing embodiments, a reference, with resistance betweenthe resistances corresponding to a pair of adjacent logical states, isstored in multiple reference cells; a “vote” unit emits a clock signalwhen a majority of the reference cell read outputs transition at thevote unit. Timing units produce different binary outputs depending onwhether a data read output or the clock signal changes state first atthe timing unit. Time-based decoding provides advantages includingimproved temperature and drift resilience, improved statediscrimination, improved reliability of multibit PCM, and fast andreliable sensing.

Modifications and Variations

As will be recognized by those skilled in the art, the innovativeconcepts described in the present application can be modified and variedover a tremendous range of applications, and accordingly the scope ofpatented subject matter is not limited by any of the specific exemplaryteachings given. It is intended to embrace all such alternatives,modifications and variations that fall within the spirit and broad scopeof the appended claims.

In some contemplated embodiments, intermediate reference currents can becreated by varying the capacitance of a reference bit line. In onecontemplated embodiment, two reference bit lines in complementary statescan be shorted together to create an intermediate reference current.

In some embodiments, it is preferable that capacitance be substantiallythe same on bitlines with read outputs being compared to the samesignal(s) (e.g., clock signal(s)), e.g., in time-based single-endedsensing; or the same within groups of bitlines with read outputs beingcompared to each other, e.g, in time-based differential sensing.

In some embodiments, it is preferable that capacitance be substantiallythe same on most or all bitlines.

In some embodiments, bitlines with different circuit capacitances aresensed by sense amplifiers with different sense threshold voltages.

In some embodiments, sense amplifiers and write heads are instantiatedin separate units.

In some embodiments, references are stored in more or fewer than threePCM cells.

In some embodiments, references are stored in a resistance trim.

In some embodiments, references are stored in PCM cells that are writtencontemporaneously with the PCM cells they are used to discriminate.

In some embodiments, Vote units receive more than three sense amplifierreference outputs.

In some embodiments, 3-to-1 Vote units use a different circuitarchitecture from that described hereinabove, e.g., a logical gatearrangement that does not use only NAND gates.

In some embodiments, logical states are numbered with thelowest-resistance state having the highest number; in some embodiments,logical states are numbered with the lowest-resistance state having thelowest number.

In some embodiments, Vote units output a clock signal in response toreceiving other than a majority of corresponding sense amplifierreference outputs, while maintaining the condition of not outputting aclock signal on outlier timings (e.g., earliest and/or latest) ofreceipt of sense amplifier reference outputs.

In some embodiments, multiple PCM cells can be selected from a bitlineto be read contemporaneously and/or in combination with each other.

In some embodiments, timing units do not latch a binary output until aclock signal transitions at the timing unit, at which time they latchdifferent logical states depending on whether a sense amplifier outputcorresponding to a PCM data cell has already transitioned at the timingunit.

In some embodiments, sense amplifier outputs corresponding to multibitPCM cells are current-mirrored, and multiple timing units correspondingto a single data cell receive current-mirrored copies of a correspondingsense amplifier output.

In some embodiments, timing units can incorporate decoding functions toproduce decoded binary data outputs.

In some embodiments, a Read Done signal can be delayed to allow time topropagate a clock signal that triggered the Read Done signal tocorresponding timing units. In some embodiments, delay can also be addedto, e.g., allow time for timing units to produce respective outputs.

In some embodiments, outputs of timing units can be decoded to outputbinary data corresponding to the logical states with which correspondingPCM data cells were written. In some embodiments, outputs of timingunits can be decoded to output binary data as received by the PCM memoryin one or more write requests that caused corresponding PCM data cellsto be written.

In some embodiments, time-based single-ended sensing for multibit PCMcan decode raw timing unit data (e.g., LATCH unit outputs) in-memoryand/or on-chip, or can feed out the raw timing unit data to be decodedexternally to the memory and/or the chip.

In some embodiments, references are chosen to discriminate logicalstates other than pairs of adjacent logical states.

In some embodiments, a minority of stored instances of a reference canbe replaced with a different value, e.g., data.

In some embodiments, test modes or other control functions can be usedto switch a PCM memory between time-based single-ended decoding andtime-based differential decoding.

In some embodiments, test modes or other control functions can be usedto switch a PCM memory between single bit and multibit operation.

Memory timing disclosed herein is described with respect to particularedge-triggered state change behavior; in some embodiments, differentedge-triggered, level-triggered or other state change behavior can beused.

In some embodiments, timing units latch on transition of a senseamplifier output other than the first to transition.

In some embodiments, timing units are configured to compare time oftransition of more than two sense amplifier outputs.

Additional general background, which helps to show variations andimplementations, may be found in the following publications, all ofwhich are hereby incorporated by reference: Lam, Chung. “Phase ChangeMemory: A Replacement or Transformational Memory Technology,” IEEEWorkshop on Microelectronics and Electron Devices (WMED), c. 2011. Choi,Youngdon, et al. “A 20 nm 1.8V 8 Gb PRAM with 40 MB/s ProgramBandwidth.” ISSCC 2012/Session 2/High Bandwidth DRAM & PRAM/2.5. c.2012.

Additional general background, which helps to show variations andimplementations, as well as some features which can be synergisticallywith the inventions claimed below, may be found in the following USpatent applications. All of these applications have at least some commonownership, copendency, and inventorship with the present application,and all of them are hereby incorporated by reference: U.S. patentapplication Ser. No. 13/869,108, “Cell-Generated Reference in PhaseChange Memory”; and U.S. patent application Ser. No. 13/869,338,“Multilevel Differential Sensing in Phase Change Memory”.

None of the description in the present application should be read asimplying that any particular element, step, or function is an essentialelement which must be included in the claim scope: THE SCOPE OF PATENTEDSUBJECT MATTER IS DEFINED ONLY BY THE ALLOWED CLAIMS. Moreover, none ofthese claims are intended to invoke paragraph six of 35 USC section 112unless the exact words “means for” are followed by a participle.

The claims as filed are intended to be as comprehensive as possible, andNO subject matter is intentionally relinquished, dedicated, orabandoned.

1-38. (canceled)
 39. A memory, comprising: multiple bitlines configuredto read multiple selected ones of multiple phase change memory cells byprecharging to approximately a precharge voltage and then discharging toa sense threshold voltage; multiple sense amplifiers configured tooutput when ones of said sense amplifiers detect that corresponding onesof said bitlines have discharged to said sense threshold voltage; andmultiple output units configured to output binary values depending onthe order in which sense amplifier outputs change state at correspondingones of said output units.
 40. The memory of claim 39, whereincapacitance is substantially the same on said bitlines reading saidselected phase change memory cells.
 41. The memory of claim 39, furthercomprising one or more decode units which decode said binary values togenerate binary outputs corresponding either to logical states withwhich corresponding ones of said phase change memory cells were written,or to data contained in one or more write instructions which causedcorresponding ones of said phase change memory cells to be written. 42.The memory of claim 39, wherein said phase change memory cells aresingle bit phase change memory cells.
 43. The memory of claim 39,wherein different ones of said output units are configured to receivedifferent pairs of said sense amplifier outputs. 44-75. (canceled)
 76. Amemory, comprising: reading together multiple groups of at least twophase change memory storage cells, cells in ones of said groups of cellsconfigured to store different logical states that are unique within saidgroup of cells to define a collective state of said group of cells;sensing read outputs of said storage cells using multiple correspondingsense amplifiers; generating sense amplifier outputs at times at leastpartially dependent on the states stored by said storage cells and saidreference cells; and outputting binary values, ones of said binaryvalues depending on which of a pair of said sense amplifier outputscorresponding to cells in one of said groups of cells first changesstate at ones of multiple output units.
 77. A memory, comprising:reading together multiple groups of at least two memory storage cells,cells in ones of said groups of cells configured to store differentlogical states that are unique within said group of cells to define acollective state of said group of cells; sensing read outputs of saidstorage cells using multiple corresponding sense amplifiers; generatingsense amplifier outputs at times at least partially dependent on thestates stored by said storage cells and said reference cells; andoutputting binary values, ones of said binary values depending on whichof a pair of said sense amplifier outputs corresponding to cells in oneof said groups of cells first changes state at ones of multiple outputunits; wherein multiple bitlines are used to read cells in a group ofcells being read, and wherein capacitance is substantially the same onsaid bitlines.
 78. The memory of claim 76, further comprising decodingsaid binary values to generate binary outputs corresponding either tological states with which corresponding ones of said phase change memorycells were written, or to data contained in one or more writeinstructions which caused corresponding ones of said phase change memorycells to be written.
 79. The memory of claim 76, further comprising:performing said reading by precharging ones of multiple bitlines toapproximately a precharge voltage and then discharging said readingbitlines to a sense threshold voltage; wherein said generating senseamplifier outputs occurs when corresponding ones of said bitlines aredetected as having discharged to said sense threshold voltage.
 80. Thememory of claim 76, wherein said phase change memory cells are singlebit phase change memory cells.
 81. The memory of claim 76, wherein saidbinary values are decoded externally to the memory. 82-113. (canceled)